1. Field of the Invention
The present invention is related to high speed interfaces.
2. Background Art
Double Data Rate (DDR) Dynamic Random Access Memories (DRAMS) are used in many systems, such as chips in set top boxes. For a DDR DRAM to interface with a chip, clock and strobe signals should be positioned accurately within address, control, and data signals. In DDR clock cycles there are two data signals per cycle, one per half cycle. It is usually desired to strobe data when the data cycle is stable within the half cycle, for example in the middle of the half cycle. Strobing a data signal at a stable point is needed to read or write data correctly to the DDR DRAM.
Conventional systems use delay lines to produce delay in the strobe signal clock to position the strobe signal. This can be done using a multiplexer (MUX) and buffers that can generate a variable number of delays. A chain of buffers (or inverters) are used for each delay, for example, one buffer may provide 10 ps of delay, 2 buffers 20 ps, etc. The MUX has paths for one, two, three, etc. intervals of delays, so the strobe signal can be delayed by, for example, 10 ps, 20 ps, 30 ps, etc. depending on a path chosen in the MUX. Another example is a delay locked loop (DLL) design, typically a digital DLL, that uses chains of buffers in delay lines to advance locked delays, for example a quarter cycle delay may be used to delay the strobe signal.
The buffers operate as desired until data rates reach 133-150 MHz. Although the buffers give some coarseness and are not ideally controlled, they are sufficient for lower data rate implementations (e.g., below 200 MHz). However, buffer delay elements do not have ideal process, temperature, and voltage (PTV) variation controls, so their output values can vary based on these factors. Another problem is that at higher data rates (e.g., 200 MHz and above), a window for reading and writing data is smaller, for example at 200 MHz the window is 2.5 ns compared to 3.5 ns at 133 MHz. So, the accuracy of the positioning of the strobe needs to be very accurately controlled at higher data rates. However, buffers can be non-ideal at these data rates, and may not accurately position the strobe signal with respect to the data signal.
Therefore, what is needed is a logic circuit, integrated circuit and method that can allow for strobe signal positioning at higher data rates, which also substantially reduces or eliminates strobe signal re-positioning that can be caused by variations in process, temperature, and/or voltage.